Computer motherboards typically provide, among other things, a system bus and an input/output (I/O) bus. The system bus supports very high speed data exchanges and is used, for example, to interface one or more central processing units (CPUs) with a main memory or a main memory controller. The I/O bus generally interfaces with the system bus via a bus bridge and is used to exchange data with one or more I/O devices such as SCSI devices, network cards, graphics cards and the like. In computer systems having only a single I/O bus, multiple I/O devices must share the common I/O bus.
In high-performance computer systems, more than one I/O bus is sometimes provided. Such multi-I/O-bus configurations yield higher performance than conventional systems because they reduce the ratio of I/O devices to I/O buses. This in turn increases the available I/O bus bandwidth per I/O device. One illustrative example of such a multi-I/O-bus configuration is the “ropes” architecture developed by Hewlett-Packard Company and described in U.S. Pat. No. 6,311,247, which patent is hereby incorporated in its entirety.
In the ropes architecture, the system bus connects to a single system bus interface device, and the system bus interface device connects to multiple peripheral component interconnect (PCI) interface devices. In particular, separate intermediate buses called “rope” buses are used to couple the PCI interface devices to the system bus interface. The rope buses exchange data using fewer bits per bus clock than does the system bus. For example, the system bus might exchange data using one hundred or more bits per system bus clock (and commensurately as many data wires), while a rope bus might exchange data using ten bits per rope bus clock (using fewer data wires than the system bus uses).
In one configuration of the ropes bus architecture, each rope bus supports a separate PCI bus. In another configuration, two or more rope buses cooperatively support a single PCI bus. In the latter arrangement, the total bandwidth available for data exchanges over the single PCI bus is increased because more than one rope bus is dedicated to the single PCI bus. In either arrangement, however, the correspondence between PCI interface devices, rope buses, and PCI buses is fixed at the time of motherboard manufacture.